DOCUMENT NO.
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STANDARD
NAME
SPECIFICATION FOR APPROVAL
00 14/16
Table_15 Cursor/Display shift
S/C R/L Cursor shift Display shift
0 0 Move one character to the left No shift
0 1 Move one character to the right No shift
1 0 Shift one character to the left with display Shift one character to the left
1 1 Shift one character to the right with display Shift one character to the right
6.2.6 Function Set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 1 N × BR1 BR0 20H to 3FH
× : Don’t care
RS=0, /CS=0, /WR=0 to 1
This instruction initializes the system, and must be the first instruction executed after power-on.
The N bit selects between 1-line or 2-line display.
N = 1 : Select 2 line display( Using anode output A1 to A80)
N = 0 : Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level.)
BR1, BR0 flag is control to brightness of VFD to modulate pulse width of Anode output as follows.
BR1 BR0 Brightness
0 0 100%
0 1 75%
1 0 50%
1 1 25%
6.2.7 Set CG-RAM Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
40H to 7FH
RS=0, /CS=0, /WR=0 to 1
This instruction
(1) Load a new 6-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to address CG-RAM.
Once “Set CG-RAM Address” has been executed, the contents of the address counter (ACC) will be
automatically modified after every access of CG-RAM, as determined by the “Entry Mode Set” instruction.
The active width of the address counter (ACC), when it is addressing CG-RAM, is 6 bits, so the counter
will wrap around to 00H from 3FH if more than 64 bytes of data are written to CG-RAM.
6.2.8 Set DD-RAM Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 ADD 80H to AFH (1-line)
C0H to E7H (2-line)
RS=0, /CS=0, /WR=0 to 1
0 1 ACG
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